Semiconductor memory device

ABSTRACT

A noise resistant static memory device is presented which is capable of reading correct data from the memory cells even in the presence of a sharp pulse noise. This is achieved by providing a signal change detection circuit which detects that a extraneous signal having a very short pulse width has been included in the read out data. In the conventional design based on auto power-down system, this type of sharp pulse will result in the destruction of the latched data because of automatic resetting of the memory read out circuit. In the invented device, resetting is nullified simultaneously with the detection of the noise signal, thereby enabling the data read out circuit to read the data again, thereby enabling to repeat the reading step. The device thus provides noise-resistant reliable memory read out performance.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to static semiconductor memorydevices, such as static RAM, and relates in particular to a memorydevice which performs stably even if noise is superimposed on thereadout control signal.

2. Technical Background of the Invention

Semiconductor memory devices, such as static RAM, are known to utilizeinternal synchronization method to reduce the power consumption for itsoperation. The internal synchronization method is a method in which theperipheral circuits of the memory cells are operated, for each change inthe address memory, only during a fixed interval of time based on a basepulse signal. This method requires an address change detection circuitATD which detects a change in the address signal and generates the abovementioned base pulse signal.

Another technique belonging to the internal synchronization methodaiming to further reduce the power consumption is known as a pulse drivemethod. This method is based on pulse driving of the circuits for afixed time interval, such as word line connected to the memory circuitand the sense amplifier circuit connected to the word line for detectingthe data read from the memory cells, in accordance with the base pulsesignal generated by the address change detection circuit ATD. Thismethod is referred to as the word line pulse driving method, or the autopower-down method, and is effective for reducing the power consumptionof static RAM devices, for example.

FIG. 9 is a schematic circuit diagram for an example of the controlcircuit 10 using the auto power-down method for devices such as staticRAM . This control circuit 10 is provided with pulse width amplifiers 30and 40. The pulse width amplifier 30 receives the signal via a buffer102, and outputs signals of pulse widths governed by the delaycapacitances C1-C3. The pulse width amplifier 40 receives the signal viaa buffer 123, and outputs signals of pulse widths governed by the delaycapacitance C4.

The operation of the control circuit 10 for memory readout will beexplained with reference to FIG. 10. When there is a change in theexternally supplied address signal ADDRESS, then address changedetection circuit ATD (not shown) generates a address change signal ATP₁-ATP_(n) in accordance with this change. The address change signals ATP₁-ATP_(n) are synthesized through the switching elements 1-13 shown inFIG. 9, and inputted into the control circuit 10. The signals areinputted into the pulse width amplifier 30 or 40, through the respectivebuffer 102 or 123, which generate control signals APD', ATDS' havingamplified signal widths as illustrated in FIG. 10.

The control signals APD', ATDS' are used to control various signalswhich control the overall operations of the static RAM device. Forexample, the control signals APD', ATDS' along with write enable signalsWE', WE and chip select signals CS', CS are inputted into the signalgeneration circuit shown in FIGS. 4 to 6, and generate signals SAON,DOC, LAT and LAT'. The signal generation circuit shown in FIG. 4consists of a NAND gate 400 and a buffer 401, and generates a controlsignal SAON for controlling the ON-OFF actions of sense amplifiercircuit 50 (to be explained later) in accordance with the signals WE',ATDS' and CS supplied thereto. The signal generation circuit shown inFIG. 5 consists of buffers 500, 503 and NAND gates 501, 502, andgenerates a signal DOC. The signal generation circuit shown in FIG. 6consists of NAND gates 600, 601 and buffers 602, 603, and generatesignal LAT, LAT'. The signals DOC, LAT, LAT' are used to control theoperation of the data output circuit 60 (to be explained later) shown inFIG. 7. When reading out data from the memory cells, the signals WE' andCS are at the high level "H" while the signals WE, CS' are at the lowlevel "L".

As shown in FIG. 10, when the address signal ADDRESS changes, thecontrol signal APD' changes from the low level (henceforth referred toas the L level) to the high level (henceforth referred to as the Hlevel) while the control signal ATDS' changes from the H level to the Llevel. Therefore, as shown in FIG. 10, the signals SAON, DOC, LAT'change respectively to the L level, and the signal LAT changes to the Hlevel.

At this time, the sense amplifier circuit 50 (refer to FIG. 7) becomesoff state in response to signal SAON, and the P-channel pulluptransistors 300, 301 both become on state, causing both output signalsSO, SO' from the sense amplifier circuit 50 to be charged to the Hlevel. Here, the clocked inverter 302, 303 supplied with the signals SO,SO' become non-transmitting in response to signal LAT' while the clockedinverter 306, 307 becomes transmitting in response to signal LAT. Atthis time further because the signal DOC is at the L level, the inputsignals GP, GN to the data outputting circuit 60 are both set to the Llevel. Accordingly, the P-channel transistor 350 and the N-channeltransistor 351, which constitute the output driver of the dataoutputting circuit 60, both become off state, and the output terminalOUT becomes high impedance state.

Next, when the above mentioned signal ATDS' changes from the L level tothe H level, the signals SAON, DOC and LAT' change from the respective Llevel to the H level, and the signal LAT changes from the H level to theL level. In this case, the sense amplifier circuit 50 (refer to FIG. 7)becomes on state because the signal SAON is at the H level, and theP-channel pullup transistors 300, 301 both become off state. Therefore,the output signals SO, SO' of the circuit 50 are supplied with the dataread out from the memory cells. At this time, the clocked inverter 302,303 become transmitting, and the clocked inverter 306, 307 becomenon-transmitting. Here, because the signal DOC is at the H level, one ofeither the signals GP or GN changes from the L level to the H level inaccordance with the data read out from the memory cells. As a result,one of the P-channel transistor 350 or the N-channel transistor 351becomes on state, and the data from the memory cells are outputted tothe output terminal OUT.

Next, after the address signal ADDRESS changes as described above and agiven time interval has elapsed, and suppose that the control signalAPD' changes from the H level to the L level, and the signal ATDS'changes from the H level to the L level. Accordingly, both controlsignals SAON, LAT' change from the H level to the L level, and thesignal LAT changes from the L level to the H level. When such changestake place, the sense amplifier circuit 50 shown in FIG. 7 becomes offstate, and the P-channel pullup transistor 300, 301 becomes on state.Therefore, the output signals SO, SO' are again set to the H level. Thismeans that the power consumption in the sense amplifier circuit 50 isshut down.

Further, in such a condition of the circuit, the clocked inverter 302,303 are non-transmitting, and the clocked inverter 306, 307 aretransmitting. The signal DOC maintains the H level state, the inputsignals GP, GN in the data outputting circuit 60 remain in latched withthe data from the memory cells. Therefore, one of either the P-channeltransistor 350 or the N-channel transistor 351 maintains the on state,and the data from the memory cells continue to be outputted to outputterminal OUT.

In the memory devices based on the above described conventional autopower-down system, the pulse widths of the control signals APD', ATDS'are determined by the pulse width amplifier 30, 40 (refer to FIG. 9). Itis essential that these signals APD', ATDS' be structured such that thememory cell data can be read out correctly even when a false data, forexample noise, represented by A' in FIG. 10 is generated during a changein the address signal ADDRESS. To cope with such problems, the controlcircuit 10 shown in FIG. 9 rapidly switches the control signal APD' fromthe L level to the H level, by utilizing a number of transistors 108-110to charge or discharge the nodes of the pulse width amplifier 30.Accordingly, the auto power-down system is rapidly reset to enablerepeated reading out of the correct data in accordance with the correctaddress signal A which follows the false address signal A' caused by thenoise. The series of events are illustrated in the latter half of FIG.10.

However, delay capacitances C1, C2 and C3 are connected to the nodes ofthe pulse width amplifier 30 for controlling the pulse width of thecontrol signal APD. Therefore, to completely reset the auto power-downmode, it is necessary to completely charge or discharge all of thenodes. In other words, in the node B shown in FIG. 10, it becomesnecessary to have a pulse signal of a pulse width which maintains the Hlevel for a specific time interval or duration (designated by T1).

For example, if a noise A' such as the one shown in FIG. 11 appears inthe address signal ADDRESS a pulse signal having a pulse width less thanT1 is created in the node B (shown in amplifier 30 circuit in FIG. 9).This phenomenon prevents complete charging or discharging of each nodein the pulse width amplifier 30, thus generating a control signal APD ofa short width. When such a control signal APD having a short pulse widthis generated, the control signal ATDS' outputted from the pulse widthamplifier 40 (refer to FIG. 9) maintains the L level. In response tosuch changes in the control signals APD', ATDS', the output signals fromeach of the signal generating circuits shown in FIGS. 4 to 6, behave asillustrated in FIG. 11. That is, signals SAON, LAT' maintains the Llevel and the signal LAT maintains the H level, and only the signal DOCbecomes the L level signal having a short pulse duration.

In such a condition, the sense amplifier circuit 50 and the dataoutputting circuit 60 behave as follows. Because the signal SAON becomesthe L level, the sense amplifier circuit 50 retains the off state. Thesignal LAT' and the signal LAT remain at the L level, therefore, theclocked inverter 302, 303 become non-transmitting while the clockedinverter 306, 307 remains transmitting. At this time, the dataoutputting circuit 60 is inputted with the latched data read out fromthe memory cells, and one of either the P-channel transistor 350 or theN-channel transistor 351 is retained in the on state. As a result, thedata read out from the memory cells are continued to be outputted to theoutput terminal OUT.

In this condition, if an L level signal is generated only in the signalDOC, the latched data in the signals GP, GN to be inputted to the dataoutputting circuit 60 are destroyed, and both signals GP, GN are resetto the L level. Therefore, the P-channel transistor 350 and theN-channel transistor 351 both become off state, and this created theproblem that ultimately the readout data could not be outputted from theoutput terminal OUT.

The static semiconductor memory device of the present invention wasdeveloped in view of the problems of the existing memory devices asdescribed above, and the objective is to present a highly reliablememory device which is unaffected by external as well as internalnoises.

SUMMARY OF THE INVENTION

A semiconductor memory device is presented for reading data quickly andreliably without being affected by internal and external noises,comprising:

(a) address change detection circuit means for detecting a change in anaddress signal and generating a change signal representing said changein address signal;

(b) control circuit means for generating a first control signal and asecond control signal to instruct data read out in accordance with saidchange signal;

(c) read out circuit means activated by said first control signal forreading out data from memory cells in accordance with said first controlsignal, and

(d) outputting circuit means for latching said output data from saidread out circuit means and outputting latched data in accordance withsaid second control signal;

wherein said device further comprises:

(e) reset nullifying circuit means for detecting changes at least insaid second control signal and generating a reset nullifying signal andsupplying said reset nullifying signal to said control circuit means,wherein said control circuit means nullifies a reset state uponreceiving said reset nullifying signal, and generate said second controlsignal of a specific pulse width.

According to the memory device of such a configuration, if the controlcircuit device is reset by a noise effect, and generates the secondcontrol signal having a pulse width less than a specific value, thereset nullifying device detects the change in the second control signaland generates a reset nullifying signal, and forwards the resetnullifying signal to the control circuit device. The control circuitdevice, upon receiving the reset nullifying signal, nullifies its resetstate, and generates another second signal having the specific pulsewidth value. Therefore, the output circuit device is able to outputcorrect data without destroying the latched data, and is able to resumenormal operation. Even if the noise is such as to destroy the latcheddata, the correct data can be read out again after the reset isnullified. The device is thus noise resistant and provides reliableperformance.

BRIEF EXPLANATION OF THE DRAWINGS

FIG. 1 is a circuit diagram for the control circuit 10 of a firstembodiment of the present invention.

FIG. 2 is a circuit diagram for the control circuit 10 of a secondembodiment of the present invention.

FIG. 3 is a circuit diagram for the control circuit 10 of a thirdembodiment of the present invention.

FIG. 4 is a circuit diagram for signal generating circuit for a signalSAON.

FIG. 5 is a circuit diagram for signal generating circuit for a signalDOC.

FIG. 6 is a circuit diagram for signal generating circuit for signalsLAT, LAT'.

FIG. 7 is a diagram showing sense amplifier circuit 50 and dataoutputting circuit 60.

FIG. 8 presents the waveforms for explaining the operation of the firstembodiment.

FIG. 9 is a circuit diagram showing the conventional type of controlcircuit 10.

FIG. 10 presents waveforms for explaining the readout operations in theconventional type of control circuit 10.

FIG. 11 presents waveforms for explaining the readout operations in theconventional type of control circuit 10 when noise is introduced.

PREFERRED EMBODIMENTS OF THE INVENTION

Preferred embodiments of the invention will be explained in thefollowing with reference to the drawings.

FIG. 1 is a circuit diagram for the control circuit 10 according to thefirst embodiment of the invention. The control circuit 10 shown here isapplicable to memory devices, such as static RAM, using the autopower-down method which operates similar to the method describedearlier. The difference between the invented circuit shown in Figuresand the conventional system shown in FIG. 9 is the provision of thesignal change detection circuit 20 which will be described in furtherdetail later. The function of the signal change detection circuit 20 isto detect a change in the control signal APD outputted from the controlcircuit 10 from the L level to the H level, and to nullify the resetstate (to be described later) of the control circuit 10 when the changeis detected.

The subsequent stages of the control circuit 10 shown in FIG. 1 areprovided with the signal generation circuits shown in FIGS. 4 to 6 as inthe conventional devices. Further, the signals SAON, DOC, LAT and LAT'generated by these signal generating circuits are supplied to the senseamplifier circuit 50 and to the data outputting circuit 60, and areconfigured to read out data in accordance with the address signalADDRESS. In other words, the normal reading operation in the firstembodiment is the same as that shown in FIG. 10.

Next, the reading operation of the control circuit 10 when noise issuperimposed on the address signal ADDRESS will be explained withreference to FIG. 8. In such a case, a false address data A' in theaddress signal ADDRESS is generated. In the conventional system, thisleads to a generation of a pulse signal having a pulse width less thanT1 at node B (refer to FIG. 9) which produced a control signal APD' of ashort pulse width, disabling the outputting operation of the readoutdata from the output terminal OUT of the data outputting circuit 60. Thesignal change detection circuit 20 in the first embodiment of thepresent invention is provided to resolve this difficulty. The followingexplains the operation of the invented memory device when a pulse of apulse width shorter than T1 is generated at the node B shown in FIG. 1due to a line noise for example. This noise pulse corresponds to thefalse address data A' shown in FIG. 8.

In the circuit configuration shown in FIG. 1, when a pulse of H levelhaving a pulse width shorter than T1 appears at the node B in thecontrol circuit 10, the pulse width amplifier 30 is unable to performcomplete charging or discharging of all the nodes. However, when thecontrol signal APD' changes from the L level to the H level, such achange is detected by the signal change detection circuit 20 whichgenerates a reset nullifying signal having a sufficient pulse width (sayT2).

This reset nullifying signal places switching elements 5 disposed in theearlier stages of the control circuit 10 in the on state. The result isthe pulse width amplifier 30 is given a pulse signal having sufficientpulse duration (width) to enable complete charging or discharging of allthe nodes. Therefore, the pulse width amplifier 30 outputs a controlsignal APD' of the correct pulse width as shown in FIG. 8. The controlsignal ATDS' changes from the L to H level when the control signal APD'changes from the L to H level. The control signal ATDS' changes from theH to the L level when the control signal APD' changes from the H to Llevel. The end results is that at the stage of the control signal APD'changing from the L to H level, the entire static RAM device of thefirst embodiment changes from the reset state to the active state. Inother words, the reset state has been nullified by the reset nullifyingsignal. Accordingly, even if a false address data A' appears, thereadout operation to read the data from the memory cell can be resumed.

Next, when the control signals APD' and ATDS' change from L to H level,the signal DOC maintains the H level, the signals SAON, LAT' change fromL to H level, and the signal LAT changes from H to L level. Accordingly,the sense amplifier circuit 50 shown in FIG. 7 becomes on state, and theP-channel pullup transistor 300, 301 becomes off state. The result isthat the signals SO, SO' outputted from the sense amplifier circuit 50correspond to the data read out from the memory cells.

Next, in this condition, clocked inverter 302, 303 become transmitting,and the clocked inverter 306, 307 become non-transmitting. At thisstage, because the control signal DOC is in the H level, one of eitherthe GP signal or the GN signal changes from the L to H level dependingon the content of the data read out from the memory cells. Accordingly,one of either the P-channel transistor 350 or the N-channel transistor351 (which constitute the output driver of the data outputting circuit60) becomes on state. The result is that data read out from the memorycells is outputted to the output terminal OUT. Even if noise shown bydotted line in FIG. 8 is generated in the signal DOC, the senseamplifier circuit 50 maintains the on state, and outputs data read outof the memory cells, the data reading operation can be continued withoutany interference from the noise signal.

Next, after a specific time interval has elapsed, the control signalAPD' changes from H to L level, and the control signal ATDS' changesfrom H to L level as shown in FIG. 8. Next, in accordance with suchchanges, the signals SAON, LAT' change from H to L level, and the signalLAT changes from L to H level. In this condition, the sense amplifiercircuit 50 shown in FIG. 7 becomes off state, thus making the P-channelpullup transistors 300, 301 to be in the on state. Accordingly, theoutput signals SO, SO' from the sense amplifier circuit 50 are chargedto the H level. The power consumption of the sense amplifier circuit 50is reduced at this stage, thus providing the auto power-down modeoperation.

Furthermore, the clocked inverters 302, 303 which are supplied withsignals SO, SO' become non-transmitting while the clocked inverters 306,307 become transmitting. Here, the control signal DOC remains at the Hlevel, the input signals GP, GN become latched state to the data readout from the memory cells. The result is that one of either theP-channel transistor 350 or the N-channel transistor 351 remains in theon state, and the read out data continue to be outputted from the outputterminal OUT.

According to the first embodiment presented above, when a noise signalis superimposed on internal signals such as address signal ADDRESS, thecircuits are arranged so that the control circuit 10 is released fromthe reset state synchronously with the detection of the noise signal bythe signal change detection circuit 20. Subsequently, the normal readingoperation is carried out without any interference, therefore, even ifnoise is generated and the data from the memory cells is destroyed inthe control circuit 10, the reset state is nullified thus enabling thedata to be read again. Therefore, the invented memory device providesnoise-resistant reading operation of high reliability.

In the first embodiment presented, a change in the control signal APD inthe control circuit 10 are detected by the signal change detectioncircuit 20. However, the same effect can be produced by a secondembodiment shown in FIG. 2, which is designed to detect a change eitherin the internal signal within the control circuit 10 or in the internalnodes (for example node B). In other word, it is possible to replace thecontrol signal APD inputted into the signal change detection circuit 20in the first embodiment, with a signal from node B to detect signalchanges. The same effect as in the first embodiment is obtained byadopting an arrangement, as shown in a third embodiment in FIG. 3, whichutilizes the signal change detection circuit 20 for detecting changes inthe address change signal ATP₁ -ATP_(n).

In the first embodiment, during the normal reading operation without thesuperimposed noise, when the pulse width of the generated pulse signalbecomes the same as that of the address change signals ATP₁ -ATPn, itleads to undesirable lengthening of the access time for accessing thedata in the memory cells. This problem can be readily rectified bymaking the pulse width of the reset nullifying signal generated from thesignal change detection circuit 20 shorter than that of the addresschange signal ATP₁ -ATP_(n) as well as by setting the terminal ends ofboth pulse signals at the same timing or by advancing the down timingfor the trailing edge of the pulse of the reset nullifying signal.

What is claimed is:
 1. A semiconductor memory device comprising:(a)address change detection circuit means for detecting a change in anaddress signal and generating a change signal representing said changein address signal; (b) control circuit means for receiving said changesignal and generating a first control signal and a second control signalto instruct data read out in accordance with said change signal; (c)read out circuit means activated by said first control signal forreading out data from memory cells in accordance with said first controlsignal, and (d) outputting circuit means for latching said output datafrom said read out circuit means and outputting latched data inaccordance with said second control signal;wherein said device furthercomprises: (e) reset nullifying circuit means for detecting changes atleast in said second control signal, and generating a reset nullifyingsignal and supplying said reset nullifying signal to said controlcircuit means, whereupon said control circuit means nullifies a resetstate, and generate another second control signal of a specific pulsewidth.
 2. A semiconductor memory device as claimed in claim 1, whereinsaid reset nullifying circuit means detect an internal signal of saidcontrol circuit means or changes in said change signal, and generatesaid reset nullifying signal.
 3. A semiconductor memory device asclaimed in claim 1, wherein a pulse width of said reset nullifyingsignal is shorter than a pulse width of said change signal.
 4. Asemiconductor memory device as claimed in claim 1, wherein said resetnullifying signal and said change signal are generated so as tosynchronize the terminal ends of both signals.
 5. A semiconductor memorydevice as claimed in claim 1, wherein the trailing edge of said resetnullifying signal changes earlier in time than the trailing edge of saidchange signal.